The invention relates to a method of manufacturing a semiconductor device with MOS capacitors and, more particularly, to an improvement of a MOS capacitor manufacturing method.
Because of a demand of high integration of semiconductor integrated circuit, it has recently been attempted to reduce the element size. In a MOS dynamic RAM (random access memory) in which a MOS capacitor to store data is formed by laying a capacitor electrode 3 on a main surface of a semiconductor substrate 1 with an insulating film 2 interposing therebetween, as shown in FIG. 1, the integration of the integrated circuit may be improved by reduction of an area of the capacitor electrode 3. However, when the electrode 3 area is reduced, the number of charges stored in the capacitor is decreased to a lower noise margin. There are proposed the following two methods to solve this defect:
(1) To increase the capacity of the MOS capacitor by thinning the insulating film. PA1 (2) To increase the capacity of the MOS capacitor by using an insulating film with a dielectric constant larger than that of an SiO.sub.2 film conventionally used for the insulating film. Such a large dielectric constant film is, for example, an Si.sub.3 N.sub.4 film.
Either method has a problem. The film used has a low breakdown voltage and a low quality (e.g. presence of pin holes). Therefore, there is a limit in making the capacitor electrode area small.
There is another method to increase the capacity of the MOS capacitor, which is known as concaved MOS capacitor method (or VMOS capacitor method). In this method, a V-shaped concaved part 4 is formed in a semiconductor substrate 1 and a capacitor electrode 6 is formed in the concaved part 4 through an insulating film 5, as shown in FIG. 1. According to this method, the effective area of the MOS capacitor may properly be selected by changing the depth or shape of the concaved part 4. Further, there arises no problem mentioned above. In forming the concaved MOS capacitor by the method, however, it is difficult to form the capacitor electrode 6, self-aligning with the concaved part 4. For this reason, margins A must be provided on both sides of the concaved part 4 for avoiding the misalignment in masking. The provision of the marginal portions interferes with reduction of the MOS capacitor and provides a serious problem in realizing high integration of the MOS dynamic RAM.